1. Field of the Invention
The present invention relates to content addressable memory (CAM) cells. More specifically, the present invention relates to six transistor CAM cells and methods for operating these cells in an array.
2. Discussion of Related Art
CAM cells are defined as memory cells that are addressed in response to their content, rather than by a physical address within an array. FIG. 1 is a block diagram of a conventional memory array formed using twelve CAM cells. The CAM cells are labeled M.sub.X,Y, where X is the row of the array, and Y is the column of the array. Thus, the array includes CAM cells M.sub.0,0 to M.sub.2,3. Each of the CAM cells is programmed to store a data value. In the described example, the data value stored in each CAM cell is indicated by either a "0" or a "1" in brackets. For example, CAM cells M.sub.0,0, M.sub.0,1, M.sub.0,2 and M.sub.0,3 store data values of 0, 1, 0 and 0, respectively. Each row of CAM cells is coupled to a common match line. For example, CAM cells M.sub.0,0, M.sub.0,1, M.sub.0,2 and M.sub.0,3 are coupled to match line MATCH.sub.0.
The array of CAM cells is addressed by providing a data value to each column of CAM cells. Thus data values D.sub.0, D.sub.1, D.sub.2 and D.sub.3 are provided to columns 0, 1, 2 and 3, respectively. Note that inverted data values D.sub.0 #, D.sub.1 #, D.sub.2 # and D.sub.3 # are also provided to columns 0, 1, 2 and 3, respectively. If the data values stored in a row of the CAM cells match the applied data values D.sub.0, D.sub.1, D.sub.2 and D.sub.3, then a match condition occurs. For example, if the data values D.sub.0, D.sub.1, D.sub.2 and D.sub.3 are 0, 1, 0 and 0, respectively, then the data values stored in the CAM cells of row 0 match the applied data values. Under these conditions, the MATCH.sub.0 signal is asserted high. Because the applied data values D.sub.0, D.sub.1, D.sub.2 and D.sub.3 do not match the data values stored in the CAM cells of rows 1 or 2, the MATCH.sub.1 and MATCH.sub.2 signals are de-asserted low. The match signals MATCH.sub.0 -MATCH.sub.2 can be used for various purposes, such as implementing virtual addressing, in a manner known to those skilled in the art.
Many different types of CAM cells have been designed. One important consideration in the design of a CAM cell is the number of transistors required to implement the cell. In general, it is desirable to have a CAM cell that is implemented using a relatively small number of transistors, such that the layout area of the CAM cell is minimized. However, there are problems associated with implementing a CAM cell using a small number of transistors.
FIG. 2 is a circuit diagram of a pair of conventional six transistor CAM cells 10 and 20. CAM cell 10 includes p-channel transistors 13-14 and n-channel transistors 11-12 and 15-16. Transistors 11-14 are connected to form a pair of cross-coupled inverters that store a data value. This data value is defined by the states of nodes 18 and 19. For example, if node 18 is at a logic high state, and node 19 is at a logic low state, then CAM cell 10 stores a logic "1" data value. In the described example, CAM cell 10 is programmed to store a logic "1" data value. The drains of transistors 15 and 16 are connected to nodes 18 and 19, respectively, and the sources of transistors 15 and 16 are connected to control lines 5 and 6, respectively. The gates of transistors 15 and 16 are connected to control lines 1 and 2, respectively. CAM cell 20, which includes p-channel transistors 23-24 and n-channel transistors 21-22 and 25-26, is connected in a manner similar to CAM cell 10. In the described example, CAM cell 20 is programmed to store a logic "0" data value (i.e., node 28 is low and node 29 is high). CAM cells 10 and 20 are commonly connected to control lines 5 and 6 as illustrated.
The data values stored in CAM cells 10 and 20 are compared with applied data values as follows. Data values D.sub.0 and D.sub.1 are applied to control lines 1 and 3, respectively (and inverted data values D.sub.0 # and D.sub.1 # are provided to control lines 2 and 4, respectively). In the described example, applied data values D.sub.0 and D.sub.1 are both logic high values. Control lines 5 and 6 are both held at a logic high value during the comparison operation. Under these conditions, the data value stored in CAM cell 10 matches the applied data value D.sub.0, but the data value stored in CAM cell 20 does not match the applied data value D.sub.1.
Within CAM cell 10, the logic high applied data value Do turns on transistor 15, thereby coupling node 18 to control line 5. Because both node 18 and control line 5 are held at logic high values, CAM cell 10 does not tend to change the voltage on control line 5. Also within CAM cell 10, the logic low data value D.sub.0 # turns off transistor 16, thereby de-coupling node 19 from control line 6. As a result, CAM cell 10 does not tend to change the logic high values applied to lines 5 and 6. If all of the CAM cells in the row match all of the applied data values, both lines 5 and 6 will remain at logic high values, thereby indicating that a match condition exists.
However, as described above, the logic low data value stored in CAM cell 20 does not match the logic high applied data value D.sub.1. Within CAM cell 20, the logic high applied data value D.sub.1 causes transistor 25 to turn on, thereby coupling node 28 to control line 5. Node 28 is coupled to ground through turned on transistor 22. As a result, the logic high voltage on control line 5 is pulled down. This reduced voltage on control line 5 is interpreted as a non-match condition.
A problem may exist if there are many non-matching CAM cells in the same row. In this case, all of the non-matching CAM cells pull down on control line 5. If the voltage of control line 5 becomes too low, the state of matching CAM cell 10 can flip from a logic high value to a logic low value. CAM cells 10 and 20 are described in more detail in U.S. Pat. No. 5,351,208. A similar six transistor CAM cell, in which control lines 5 and 6 are combined into a single control line, is described in U.S. Pat. No. 4,694,425.
It would therefore be desirable to have a six transistor CAM cell that is not as susceptible to disturb conditions during compare operations as the above described six transistor CAM cell.